<sec>In recent years, amorphous InGaZnO thin-film transistor (InGaZnO TFT) has attracted intensive attention. Due to its high mobility, low off-state current, and excellent uniformity over large fabrication area, the InGaZnO TFTs promise to replace silicon-based TFTs in flat panel displays, optical image sensors, touch sensing and fingerprint sensing area. The on-state performances of InGaZnO TFT are used in thin film transistor liquid crystal display, active-matrix organic light emitting display, etc. Consequently, numerous on-current models have been proposed previously. However, for lots of the emerging sensing applications such as optical image sensors, the leakage current of InGaZnO TFTs is critical.</sec><sec>Previous literature has shown that the leakage current generation mechanisms in TFTs include trap-assisted thermal emission, trap-assisted field emission, inter-band tunneling, and auxiliary thermal electron field emission containing Poole-Frenkel effect. However, up to now, there has been few reports on the leakage current model of InGaZnO TFT, which hinders further the development of emerging applications in InGaZnO TFTs for sensor and imagers integrated in display panels.</sec><sec>In this paper, the leakage current model of InGaZnO TFT is established on the basis of carrier generation recombination rate. The feasibility of the proposed model is proved by comparing the TCAD simulations with the measured results. In addition, the influences of geometrical parameters on the leakage current of InGaZnO TFT, i.e. the channel width, the active layer thickness, and the gate dielectric thickness, are analyzed in detail. This research gives insightful results for designing the sensors and circuits by using the InGaZnO TFTs.</sec>

An analytical drain current model on the basis of the surface potential is proposed for indium–gallium zinc oxide (InGaZnO) thin-film transistors (TFTs) with an independent dual-gate (IDG) structure. For a unified expression of carriers’ distribution for the sub-threshold region and the conduction region, the concept of equivalent flat-band voltage and the Lambert W function are introduced to solve the Poisson equation, and to derive the potential distribution of the active layer. In addition, the regional integration approach is used to develop a compact analytical current–voltage model. Although only two fitting parameters are required, a good agreement is obtained between the calculated results by the proposed model and the simulation results by TCAD. The proposed current–voltage model is then implemented by using Verilog-A for SPICE simulations of a dual-gate InGaZnO TFT integrated inverter circuit.