High-radix Cooley-Turkey FFT algorithms have obvious advantages: less multiplications and reduced memory accesses so power consumption can be reduced. However, the disadvantages are that traditional direct mapping implementation of high-radix butterfly element will required more complex multipliers and thus large silicon area will be consumed. In this paper, we proposed an eficient approach to realize the high radix butte rfly process element. This approach employed pipelining technics to cascade the paralleled multipliers and thus fewer complex multipliers are utilized to realize the radix-r butterfy element. This approach can achieve a good trade-off between speed and area in the design of high radix butterfly element.

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This payer presented a VLSEarcbitecture for the FFT processors--which 1~1 1~ employed the pipelined archileclure to realize the high speed radix-r Process Elements (PES) ;and glohallp utilized the high-radix shared-memory architecturi? to implement the area-efficient FIT processors. Based on this architecture, a high perforniance 512-point FFT procesor has k e n designed in the 0.6um 3 3 v CMOS process to demonstrated its feasibility. posed architecture. This FFT processor can computer a 5 12point FFI' \uithin 2 0~s and only the arm of 30 mm2 is consumed. ARCHITECTURE

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