As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half-SPP plasmonic material-dielectric -wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO 2 based SERS chips show an enhancement factor of 8.9 × 10 10 , 265 times higher relative to the chips with far thinner SiO 2 walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost-effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. This study demonstrates a complete generalized platform from design to low-cost batch-fabrication to applications for novel high performance SERS chips of any plasmonic materials/dielectrics.

A comprehensive study on dynamic characteristics of GaN MISHEMT with a 5nm-thick in-situ SiNx dielectric is presented. Effects of both negative and positive gate bias on threshold voltage instability were investigated and miniature threshold voltage shift was acquired. The slight shift was considered to be associated with the traps at the insulator/AlGaN interface and in the dielectric layer itself. Pulsed I-V measurements with various gate quiescent biases presented small current collapse (11%) and low enhancement of dynamic Ron for zero quiescent drain bias. When drain quiescent bias was strengthened to 20V, an increased dynamic Ron/static Ron ratio was identified but still limited to a low value of 1.24. The conduction reduction was in a good agreement with measurement results from drain current transient spectroscopy and possibly originates from trap states existed in the access region. Additional current collapse was observed in hard switching-on operation, resulted from energetic hot electrons accelerated by drain-source electrical field during the off-to-on step. The measurement results showed stabilized threshold voltage, a low dynamic Ron/static Ron ratio, and suppressed current collapse via employing a 5-nm thin in-situ SiNx layer in GaN MISHEMT, enabling it a promising solution for high-efficiency power switching applications.

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