No abstract

The repetitive unclamped inductive switching (UIS) avalanche stress are conducted to investigate the degradation and breakdown behaviors of conventional shield gate trench MOSFET (C-SGT) and P-ring SGT MOSFETs (P-SGT). It is found that the static and dynamic parameters of both devices show different degrees of degradation. Combining experimental and simulation results, the hot holes trapped into the Si/SiO2 interface and the increase of crystal lattice temperature should be responsible for the degradation and breakdown behaviors. Moreover, under repetitive UIS avalanche stress, the reliability of P-SGT overcomes that of C-SGT, benefitting from the decreasing of the impact ionization rate at bottom of field oxide caused by the existence of P-ring.