No abstract

A new type of decoder for double-error-correcting binary BCH codes is presented. The simple and regular control clock signals of the decoder can be directly extracted from the line signals. The decoder needs only n clock cycles to decode one received word, where n is the block length of the code. A (31, 21, 5) BCH decoder is used as a hardware implementation example to illustrate the operation principle. The decoder can work at a data rate of up to 3.4Mbits/sec when it is implemented in a programmable Logic Cell Array (LCA) chip.iE-jn BCH is BCH