This paper presents experimental RF characterizations and modeling on the nano-scale multi-finger gate MOSFETs of the HLMC 40 nm low-power CMOS technology. Both the resistive and capacitive components in the equivalent circuit model for the RF MOSFET devices are calibrated based on temperature-dependent S-parameter measurements (0.25 -40 GHz) from 298 K to 6 K. By integrating the intrinsic device model and the extrinsic parasitic parameters, a generic cryogenic device RF model is developed to capture the cutoff frequency and high-frequency performance of NMOS and PMOS transistors with varied device configurations. The establishment of validated database as functions of device size, temperature, and frequency responses lays a solid foundation for practical large-scale cryo-CMOS RF circuit design and optimization.
In this paper, the complex behavior of saturation drain current (I dsat ) dependence on channel width was investigated. We compared two types of devices and concluded that the variation of I dsat with changing width is determined by both the y-direction shallow trench isolation mechanical stress (y-stress) effect and the delta width effect. Moreover, a semi-empirical formula was proposed to describe the I dsat dependence on channel width, taking into account these two effects. To reduce the STI stress, we examined several process steps that may contribute to the stress development, and found that a high temperature post-liner-anneal step can obviously reduce the stress effect.
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