No abstract

Multi-patterning lithography at the 10-nm and 7-nm nodes is driving an exponential increase of metrology complexity in the overlay and alignment tree. Coupled with the highly involved process stacks required to reach these nodes, the setup and verification of the metrology recipes have reached new levels of importance. With an all-encompassing holistic mindset the authors present four node-enabling technologies using production data from a leading logic customer. Firstly an optimized layout is defined using a metric that ranks the importance of available wafer coordinate positions based on the model to be use for lithographic apparatus actuation. Next to minimize influence of process induced target asymmetry on overlay, the authors define how to find the optimum wavelength and polarization settings for overlay metrology. Once the process has reached a high volume-manufacturing (HVM) environment, we propose a method of monitoring using a single point key performance indicator (KPI). In the last section all learning is applied with integrated metrology (IM) within HVM to realize improved correctable error in measured overlay.