materials (paper, flexible); adequate device level mobility [2] that can be further optimised by engineering appropriate gate dielectrics; high transparency due to their wide band gap; the capacity for postfabrication tunable resistance (memristive effects) [3,4], and good chemical stability. These features have led to the use of MOs in a variety of applications ranging from resistive random access memories (RRAMs) [5,6] and thin film transistors (TFTs) [7,8] to oxidebased photovol taics [9] and sensors [10], introducing a new era for large area transparent/stretchable electronics [11,12] and neuromor phic systems [13,14]. It is also worth mentioning two very recently published perspective articles [15,16] AbstractThe electrical properties of thin TiO 2 films have recently been extensively exploited with the aim of enabling a variety of metaloxide electron devices: unipolar and bipolar semiconductor devices and/or memristors. In these efforts, investigations into the role of TiO 2 as active material were the main focus; however, electrode materials are equally important. In this work we address this point by presenting a systematic quantitative electrical characterization study on the interface characteristics of metalTiO 2 metal structures. Our study employs typical contact materials that are used both as top and bottom electrodes in a metalTiO 2 metal setting. This allows an investigation of the characteristics of the interfaces as well as holistically studying an electrode's influence on the opposite interface, referred to in this work as the top/bottom electrodes interrelationship. Our methodology comprises the recording of current-voltage (I-V) characteristics from a variety of solidstate prototypes in the temperature range of 300 K -350 K, and their analysis through appropriate modelling. Clear field and temperaturedependent signature plots were also obtained, so as to shine more light on the role of each material as top/bottom electrodes in metalTiO 2 metal configurations. Our results highlight that these are not conventional metal-semiconductor contacts, and that several parameters are involved in the formation of the interfacial barriers, such as the electrode's position (atop or below the film), the electronegativity, the interface states, and even the opposite interface electrode material. Overall, our study provides a useful database for selecting appropriate electrode materials in TiO 2 based devices, offering new insights into the role of electrodes in metaloxide electronics applications.

Resistive random access memories (RRAMs) are considered as key enabling components for a variety of emerging applications due to their capacity to support multiple resistive states. Deciphering the underlying mechanisms that support resistive switching remains to date a topic of debate, particularly for metal-oxide technologies, and is very much needed for optimizing their performance. This work aims to identify the dominant conduction mechanisms during switching operation of Pt/TiO2-x/Pt stacks, which is without a doubt one of the most celebrated ones. A number of identical devices were accordingly electroformed for acquiring distinct resistive levels through a pulsing-based and compliance-free protocol. For each obtained level, the switching current-voltage (I-V) characteristics were recorded and analyzed in the temperature range of 300 K–350 K. This allowed the extraction of the corresponding signature plots revealing the dominant transport mechanism for each of the I-V branches. Gradual (analogue) switching was obtained for all cases, and two major regimes were identified. For the higher resistance regime, the transport at both the high and low resistive states was found to be interface controlled due to Schottky emission. As the resistance of devices reduces to lower levels, the dominant conduction changes from an interface to the core-material controlled mechanism. This study overall supports that engineering the metal-oxide/metal electrode interface can lead to tailored barrier modifications for controlling the switching characteristics of TiO2 RRAM.

The present paper investigates the effect of stressing bias magnitude and stressing time on the discharging process in MEMS capacitive switches. The calculation of discharge current through the dielectric film is based on monitoring the rate of shift of bias for up-state minimum capacitance. The data analysis shows that the discharge current lies in the range of femto-Amperes and the calculated discharge time constant depends directly on the time window of observation and on the stressing conditions. Moreover the analysis reveals an increase of trapped charge that remains in the bulk of the dielectric film for very long time as the stressing bias increases. The dominant discharge process, taking place under an intrinsic field of about 10 3 V/cm, is found to be the hopping effect.

The emergence of memristor technologies brings new prospects for modern electronics via enabling novel in-memory computing solutions and energy-efficient and scalable reconfigurable hardware implementations. Several competing memristor technologies have been presented with each bearing distinct performance metrics across multi-bit memory capacity, low-power operation, endurance, retention and stability. Application needs however are constantly driving the push towards higher performance, which necessitates the introduction of a standard benchmarking procedure for fair evaluation across distinct key metrics. Here we present an electrical characterisation methodology that amalgamates several testing protocols in an appropriate sequence adapted for memristors benchmarking needs, in a technology-agnostic manner. Our approach is designed to extract information on all aspects of device behaviour, ranging from deciphering underlying physical mechanisms to assessing different aspects of electrical performance and even generating data-driven device-specific models. Importantly, it relies solely on standard electrical characterisation instrumentation that is accessible in most electronics laboratories and can thus serve as an independent tool for understanding and designing new memristive device technologies.

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