Built in self testing (BIST) is most attractive technique to test different kind of circuits. In BIST, test patterns are generated by different techniques of test pattern generation and applied to the circuit under test (CUT). In pseudorandom BIST architecture, test patterns are generated by Linear Feedback Shift Register (LFSR). Due to high Switching in pattern generation by conventional LFSR, power dissipation is high in conventional LFSR. Power is an important constraint in VLSI (Very Large Scale Integration) testing. This paper presents a modification in LFSR to generate pattern for BIST applications with reduced power requirement. This new technique represent low transition pattern pseudorandom generator (LT-PRG) for Test-per-Clock and Test-per-Scan BIST applications. The LT-PRPG is designed with the use of a LFSR and a 2x1 multiplexer. Experimental results show that the implementation of Bit-Swapping LFSR can reduce the internal transition activity probability which directly affect the dissipation of power in CUT without affecting the fault coverage.