This paper presents a strategy to speed-up the simulation of processors having SIMD extensions using dynamic binary translation. The idea is simple: benefit from the SIMD instructions of the host processor that is running the simulation. The realization is unfortunately not easy, as the nature of all but the simplest SIMD instructions is very different from a manufacturer to an other. To solve this issue, we propose an approach based on a simple 3-addresses intermediate SIMD instruction set on which and from which mapping most existing instructions at translation time is easy. To still support complex instructions, we use a form of threaded code. We detail our generic solution and demonstrate its applicability and effectiveness using a parametrized synthetic benchmark making use of the ARMv7 NEON extensions executed on a Pentium with MMX/SSE extensions.

International audienceVirtual prototyping of MPSoCs requires fast processor simulation models. Dynamic binary translation is an efficient technology for instruction set simulation, but as it is basically used for effortless code migration, it targets mostly general purpose processors. As many heterogeneous MPSoCs include VLIW processors, we propose and detail in this paper a strategy to perform dynamic binary translation of VLIW codes on scalar architectures for simulation purposes. Our simulation experiments show that it is a few orders of magnitude faster than direct instruction interpretation, although the translator includes no optimization