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Articles you may be interested inDetermining factor of effective work function in metal/bi-layer high-k gate stack structure studied by photoemission spectroscopy Appl. Phys. Lett. 100, 112906 (2012); 10.1063/1.3695166 Photoinduced charge-trapping phenomena in metal/high-k gate stack structures studied by synchrotron radiation photoemission spectroscopy Appl. Phys. Lett. 96, 162902 (2010); 10.1063/1.3409162 Thermally stable high effective work function TaCN thin films for metal gate electrode applications Titanium nitride (TiN) films have been used as gate electrode on metal-oxide-semiconductor (MOS) devices. TiN effective work function (EWF) values have been often reported as suitable for pMOS. For nMOS devices, a gate electrode with sufficient low EWF value with a similar robustness as TiN is a challenge. Thus, in this work, aluminum (Al) is incorporated into the TiN layer to reduce the EWF values, which allows the use of this electrode in nMOS devices. Titanium aluminum (TiAl), Al, and aluminum nitride (AlN) layers were introduced between the high-k (HfO 2 ) dielectric and TiN electrode as Al diffusion sources. Pt/TiN (with Al diffusion) and Pt/TiN/TiAl/TiN structures were obtained and TiN EWF values were reduced of 0.37 eV and 1.09 eV, respectively. The study of TiN/AlN/HfO 2 /SiO 2 /Si/Al structures demonstrated that AlN layer can be used as an alternative film for TiN EWF tuning. A decrease of 0.26 eV and 0.45 eV on TiN EWF values were extracted from AlN/TiN stack and AlN/TiN laminate stack, respectively. AlN/TiN laminate structures have been shown to be more effective to reduce the TiN work function than just increasing the AlN thickness. V C 2014 AIP Publishing LLC.

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.