Conventional three-dimensional integrated circuits (3D ICs) stack multiple dies vertically for higher integration density, shorter wirelength, smaller footprint, faster speed and lower power consumption. However, the through-silicon-vias (TSVs) in diestacking based 3D ICs are large in size (>1um) and reduce the benefits that can be attained by the technology. In this paper, we will introduce a new fabrication process that facilitates monolithic 3D die integration and yields much smaller TSVs (~50 nm). We will also discuss various design benefits brought by the monolithic 3D IC technology.