Electromigration (EM) failure statistics and the origin of the lognormal deviation (σ) for Cu interconnects have been investigated by analyzing the lifetime statistics and void size distributions at various stages during EM testing. Experiments were performed on 0.18 μm wide Cu interconnects with tests terminated after specific amounts of resistance increases, or after a specified test time. Void size distributions of resistance-based, as well as time-based EM tests were obtained using focused ion beam (FIB) microscopy. The lifetime and void size distributions were found to follow lognormal distribution functions. The σ values of EM lifetime and time-based void size distributions decrease with higher percentages of resistance increase, reaching an asymptotic value of σ ∼ 0.14. In contrast, σ values of resistance-based void size distributions are significantly smaller and do not show an obvious dependence on time. The statistics of resistance-based void size distributions can mainly be accounted for by geometrical variations of the void shape, while the statistics of time-based void size distributions requires consideration of kinetic aspects of the EM process. The σ values of EM lifetime distributions at long times can be simulated based on measured void size distributions, taking into account geometrical and experimental factors of EM. In contrast, for short times the statistics of initial void formation and the kinetics of interfacial mass transport have to be considered.

Electromigration failure statistics and the origin of the lognormal standard deviation for copper interconnects were investigated by analyzing the statistics of electromigration lifetimes and void size distributions at various stages during testing. A statistical correlation between electromigration lifetimes and void evolution was established. Using simulation to fit the experimental data, the parameters influencing the electromigration lifetime statistics were identified as variations in void sizes, geometrical and experimental factors of the electromigration experiment, and kinetic aspects of the mass transport process, such as differences in the interface diffusivity between the lines.

Crystalline silicon solar cells with copper-plated contacts are fabricated, encapsulated in ethylene-vinyl acetate (EVA), and subject to extended damp heat stress (85 C and 85% relative humidity). We source cell precursors from several different cell manufacturers and employ several different patterning methods of the silicon nitride layer and deposit a plated front contact stack of nickel, copper, and tin using light-induced plating. Across different Cu-plated samples, we find similar degradation that impacts

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An alternative seed layer (ASL) process is proposed in order to increase the efficiency of silicon solar cells by forming a low cost, front metal contact with reduced contact resistance and increased line conductivity and aspect ratio. A nickel seed layer is deposited directly on silicon to form a low resistivity nickel silicide (NiSi) ohmic contact and this contact is thickened by light induced plating (LIP) of nickel and copper. Unlike the traditional screen printing process currently used in industry, the ARC layer must be patterned to expose the silicon surface for nickel deposition.This paper investigates the compatibility of the ASL process with two different ARC patterning methods: 1) masking & wet chemical etching, and 2) laser ablation. In addition, the ASL process is demonstrated on both mono-crystalline and polycrystalline silicon substrates with ARC layers from different sources. The nickel seed layer and resulting NiSi layer are evaluated using scanning electron microscopy (SEM) with energy dispersive x-ray spectroscopy (EDS) and focused ion beam (FIB) cross section.X-ray photoelectron spectroscopy (XPS) is used to investigate the completeness of the ARC removal step. In addition, contact resistance testing will be performed to determine the quality of the ohmic contact formed from the ASL process. The importance of chemistry optimization in the development of a robust ASL process that is compatible with mono-Si and poly-Si substrates and exposed to two different ARC patterning methods will be discussed.