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This paper presents a node-parallel Viterbi decoding architecture with bit-serial processing and communication. This structure allows short constraint length decoders to be expanded, without loss of throughput, to implement a Viterbi decoder of larger constraint length. Wiring of the decoder models the encoder trellis and a variety of generating codes can be accommodated by appropriate wiring of the decoder. Bit-serial communication between processing nodes requires only a single wire and thus on chip and off chip wiring requirements are quite small. A constraint length K=4 "proof of concept" chip was developed using 9860 transistors in 3 pm CMOS. The circuit supports any rate 1/2 or 1/3 code with 8 level soft decision. Performance measurements on two rate 1/2 interconnected chips confirm the expected 3.8 dB coding gain at 10-4 error rate.