Single-Event Gate-Rupture (SEGR) in Vertical Double Diffused Metal-Oxide Semiconductor (VDMOS) power transistors exposed to a given heavy ion LET occurs at a critical gate bias that depends on the applied drain bias. A method of predicting the critical gate bias for nonzero drain biases is presented. The method requires as input the critical gate bias vs. LET for V DS = 0V. The method also predicts SEGR sensitivity to improve for larger gate-oxide thicknesses. All predictions show agreement with experimental test data.

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A physical model of hole-collection following a heavy-ion strike is proposed to explain the development of oxide fields sufficient to cause single-event gate rupture in power MOSFET's. It is found that the size of the maximum field and the time at which it is attained are strongly affected by the hole mobility. * This w a k WM supported by the Navd Surface Warfare Centar and ths Defenae Nuclear Ageocy that allows current from the external power supply to destroy the device [ 11. In the case of SEGR, the ion-generated electron-hole pairs are separated by the applied bias. For dlscussion, assume an n-channel device w i t h gate grounded and drain positively biased, as shown in Fig. 1.