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Reconfigurable computing has become an essential part of research in the domain of modern computing paradigms. Reconfigurable computing approach integrates both, the performance and flexibility gaining aspects on a single computing system. The computational performance of such kind of systems is crucially dependant on the configuration overheads caused by configuration management unit. Performance of the configuration management unit greatly accelerates the computational power of reconfigurable computing system. There are a large number of control and management techniques which can be used to improve this technology. This research paper presents a comprehensive analysis of existing performance enhancement methodologies in practice. The paper also point outs the different aspects of configuration management for critical analysis and further optimization.

The increasing needs for power consumption of computing machines is getting a worrying factor for the emerging embedded systems. Asynchronous computer architecture reduces the power consumption of the systems. They are built around using emerging concept of clock less systems. Asynchronous computing systems have demonstrated a full scaled computational performance to fulfill the emerging needs of computational intensive applications. Design and fabrication of asynchronous processing systems has emerged dramatically and the area is under close observation for more advanced research on the issues of asynchronous designs, programming, and protocols implementation, development of computational algorithms as well as fabrication of such architecture at silicon wafer level. This research paper presents the critical aspects of high design complexity, better scalable computational performance and reduction in energy obtained by using modern asynchronous computing architectures.

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In this research paper an alternative design for Reconfigurable Instruction Set Processor (RISP) has been proposed with the capability of the most optimal configuration overhead for Very Long Instruction Word (VLIW) based architectures. This processor supports the demand-driven modification of its instruction set during the program execution. The processor has been integrated with the high speed partially reconfigurable Field Programmable Gate Array (FPGA) cores as its Reconfigurable Functional Units (RFUs) in place of ALUs and it treats instructions as removable modules which can be paged in and paged out through the partial reconfigurations according to the requirements of the application being under execution. Instructions occupy the FPGA resources only when needed and FPGA resources can be released and reused at run-time on a fly for other kind of instructions belonging to the same or the different applications without affecting those who are currently under execution on the FPGA platform. RISPs are the next generation of processors which can adapt their instruction sets through a reconfiguration in their hardware according to the requirements of the applications being under execution on them. In this way the processor adapts its instruction set for the hardware design which is the most suitable for the application being executing on it, during the process of its execution and hence it accelerates the performance. RISPs are the programmable processors which contain the reconfigurable logic in one or more of their functional units. The hardware design of such a kind of processor can be categorized into two main tasks: The first task is to design the reconfigurable logic itself and the second task is to design the communication interface of reconfigurable logic with the remaining modules of the processor.