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Tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at deca-nanometer dimensions. Tunneling currents are no longer considered as unwanted parasitics in these devices. In this work, the device architecture and performance of both n-type and p-type TFETs with a channel length of 30nm are simulated and studied. Mixed mode simulation of TFET inverter and a comparison with CMOS inverter characteristics show that TFET inverter doesn't need level shifting at the output and can succeed CMOS digital applications.