This paper presents the research work towards a fully integrated 17 GHz transceiver in 0.13 prn standard CMOS. The simultaneous challenge of high-integration, highest frequency and low-voltage design is solved cornbining optimized on-chip passives and RF circuit techniques with a double-conversion sliding RF-architecture. Three measured chips clearly demonstrate the 'feasibility of a CMOS transceiver at highest frequency. A fully integrated A -C 13 GHz PLL consumes GO mW from 1.5 V supply. The complete RF RX-path features a gain of 37dB, IIPJ of -37dBm and a SSB NF of 9.3dB, consuming l8O.81nW from 1.5V supply. A first T X path testchip includes the second modulator and linear output driver. Consuming 93mW from 2.5V supply, it features a gain of 4dB and an OIP3 of I3dBm.

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An integrated front-end, for automotive and industrial applications beyond 20 GHz, in 0.13 µm standard CMOS is presented. The front-end chip includes a low noise amplifier, a transformer-based Gilbert-mixer, an intermediate frequency amplifier and a buffer for the local oscillator input. The differential front-end at 22.5 GHz, measured on test-board, achieves a gain of 25.8 dB, a SSB noise figure of 6.8 dB, an input IP3 of -34.6 dBm and an input 1 dB compression point of -41.5 dBm while consuming 112.5 mW at a power supply voltage of 1.5 V.

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