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<abstract> <p>Pulse diagnosis, also known as Nadi Pariksha, is one of the various diagnostic modalities used in Ayurveda. Nadi Pariksha is a way of determining the underlying cause of a sickness that needs extensive knowledge of the Tridosha signals (i.e. Vata, Pitta and Kapha), as well as the peculiarities of each pulse signal and their relationship to each dominant signal. A Nadi expert can gain a sense of the patient's health status by using this approach and then provide treatment based on that information. In the present day, the health monitoring of people has become an essential requirement. A system which keeps track of the patient's health and continuously captures pulse signals will be helpful. In this work a healthcare monitoring system that uses sensors was developed, and the analysis of Vata, Pitta and Kapha for various patients is discussed, as well as the uploading of the same data to a self-made IoT cloud. The mean values of Vata, Pita and Kapha were compared for different age groups; we found that it is more significant for the age group of 41‒50.</p> </abstract>

This study proposes about the autonomous navigation of a multi-robot for transportation in indoor environments. This transportation is integrated with three foldings of VLSI architectures; they are 1) shortest optimal path planning 2) behavioral control between multi-robot with leadership swapping methods as per dynamic conditions and 3) obstacle avoidance by multi-robot. The hardware schemes have been designed for navigation of multi-robot with shortest path planning, based on an extended Dijkstra algorithm along with the Delaunay triangulation method. The behavioral control mechanism between the multi-robot is another challenge at the time of navigation and obstacle avoidance at both static and dynamic conditions in real-time scenario. The leader and follower approaches are deployed for cooperation between multi-robot to accomplish the task. The VLSI architectures are proposed for multi-robot navigation in the warehouse-type indoor environment. It is developed using Verilog HDL, simulated and synthesized with Xilinx Vivado 17.1. The Zynq-7000 SoC ZC702 FPGA is used as the target device.

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