Abstract-Among the various CMOS logic families, PTL has been recognized as one of the potential alternatives to static CMOS for the synthesis of high performance and low power circuits. Moreover, as BDDs can be readily mapped to PTL circuits, use of BDDs has been synonymous with the synthesis of PTL circuits. Most of the reported works on PTL synthesis are based on the Reduced Ordered BDDs (ROBDDs). We have developed a novel heuristic-based technique for obtaining Reduced Unordered BDDs (RUBDDs), which leads to circuits of smaller size having lesser delay and smaller power consumption compared to the existing results. We propose the technology mapping using the popular LEAP-like cells, such that the PTL circuit synthesis flow has the same flavor as that of the standard cell-based static CMOS circuit synthesis. We have also developed models for the estimation of delay and power consumption of the synthesized PTL circuits and compared those with the static CMOS and other existing PTL-based circuit realizations. I IntroductionIn recent years, static CMOS has emerged as the technology of choice for VLSI circuit realization, because of the ease of design, robustness, scalability and other advantages that this logic style offers. But, static CMOS uses both pMOS and nMOS transistor networks, taking larger area, incurring more delay and higher power dissipation. As a consequence, in the present era of sub-micron technology, driven by the need for low power and high performance, researchers are looking for better alternatives. Recent studies [1]- [4] show that pass transistor logic (PTL) circuits provide superior performance in terms of area, delay and power. However, PTL circuits have some inherent limitations, such as threshold voltage drop across pass transistors, possibility of sneak paths and higher delay for cascaded pass transistors. While synthesizing PTL circuits, care should be taken to overcome these limitations.Although PTL is a promising alternative to static CMOS, it demands for a radically different logic synthesis approach. It has been observed that binary decision diagram (BDD) representation of a logic function can be readily mapped onto a PTL network. Moreover, BDD-based synthesis avoids some of the limitations mentioned above. This has made BDD-based approach very attractive for the synthesis of PTL circuits. In earlier works In this paper, we have also used decomposed BDDs for PTL circuits synthesis. In addition to using decomposed BDDs, we have used a new heuristic, based on ratio parameters (RP), for optimal variable ordering. The concept of RP was used earlier [6], [7] for the synthesis of multiplexer-based circuits. The RP-based heuristic helps in obtaining BDDs with smaller number of nodes. However, BDDs generated by this approach may not have the same ordering of variables at the same level along different paths. These BDDs may be termed as Reduced Unordered BDDs (RUBDDs), in contrast to Reduced Ordered BDDs (ROBDDs) commonly used in the existing approaches. As the size of BDDs is more importan...

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