Contemporary router/switch technology for high-performance local/system area networks (LANs/SANs) should provide the capacity to fit the high bandwidth and timing requirements demanded by current applications. The MultiMedia Router (MMR) aims at offering hardware-based QoS support within a compact interconnection component. One of the key elements in the MMR architecture is the link scheduling algorithm. This algorithm must solve conflicts among data flows that share an input physical link. Required solutions are motivated by chances for parallelization and pipelining, while providing the necessary support both to multimedia flows and to best-effort traffic. In this work, a cost-aware link scheduling based on the temperature coding of priority value associated to every head flit is presented and evaluated.This research was partially supported by the Spanish CICYT under grants No. TIC2003-08154-C06-04 and TIC2003-08154-C06-06. 1 The MultiMedia Router is devised as a link-layer interconnection element. The term "router" is inherited from the interconnection elements used in multicomputer and multiprocessor networks, rather than from the IP world.

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Abstract. In this paper we present the architecture and implementation of a hardware NIC scheduler to guarantee QoS on servers for high speed LAN/SAN. Our proposal employs a programmable logic device based on an FPGA in order to store and update connection states, and to decide what data stream is to be sent next. The network architecture is connection-oriented and reliable, based on credit flow control. The architecture scales from 4 to 32 streams using a Xilinx Virtex 2000E. It supports links with speeds in the order of Gbps while, maintaining the delay and jitter constrains for the QoS streams.

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Nowadays, high performance systemllocal area networks are filled by heterogeneous traffic, constituted by information flows with different bandwidth and latency requirements. The bottleneck existing between the network process elements speed (servers, routers,...) and the bandwidth in the links makes necessary new proposals in the design of these network components. The MMR (and its simplified version, the SMMR), a router which supports QoS, is a very well-known proposal in this area. In this article, we propose the architecture and implementation of a reprogramable and scalable traffic Generator/Monitor as support for the study, in a easy way, of this sort of routers. The Generator/Monitor is modular and has been implemented inside an FPGA using a high level hardware programming language such as the Handle-C.The result is a highly parameterizable platform, which allows prototyping the communication system of a high speed LAN/SAN environment, in order to study complexity reductions and optimizations of a router under different traffic conditions and server models.