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A coherent receiver based on silicon photonics is presented. Its performance is confirmed at 112 Gb/s with PM-QPSK modulation at 28 Gbaud up to 4800 km and at 224 Gb/s with PM-16QAM up to 640 km. The packaged core has very compact dimensions of 6mm×8mm. IntroductionHigh-speed Coherent communication systems are now deployed in long-haul links especially at 100 Gb/s and are increasingly considered as well for shorter reach. While increasing the physical density, minimizing the power consumption, heat dissipation and component size becomes a stringent requirement. Photonic integration is seen as the most promising avenue to address these problems. In particular, integration on silicon photonics (SiP) attracts enormous interest due to its potential for low cost, high level of integration and ultra-small footprint [1][2].In this paper, a coherent receiver is demonstrated using hybrid integration on silicon photonics. The potential for a very small footprint component is demonstrated by compact packaging. Good performance is confirmed by a transmission experiments at 112 Gb/s and 224 Gb/s using PM-QPSK and PM-16QAM at 28 Gbaud. DesignThe SiP chip was fabricated at ePIXfab and used for the passive part of the receiver. A standard single-mode fiber polished at an angle close to 45° is used to couple the light from the signal port to the SiP chip through a 2D surface grating coupler which also provides the polarization splitting [3]. For each polarization, a 2×4 MMI coupler (multimode interference) acts as a 90° optical hybrid that mix the signal with an optical local oscillator (LO) which is coupled from a polarization maintaining fiber to the SiP chip through a 1D surface grating coupler [4]. The outputs of each 2×4 MMI coupler are connected to 1D surface grating couplers allowing the light to emerge out of the chip and be collected by two 1×4 photodiode arrays that are flip-chip bonded on top of the SiP chip which is beforehand gold metallized. Capacitors are mounted on top of the chip and wirebonded to the photodiode cathodes for biasing purpose. The SiP chip is fixed on a ceramic substrate which allows carrying the RF signals properly. Two dual differential trans-impedance amplifiers (TIAs) are also attached on the ceramic in close proximity to the SiP chip. Their inputs are wirebonded to the photodiode anodes. Each differential TIA is connected to two photodiodes collecting the light from two out-of-phase outputs of a MMI coupler, thus providing balanced detection. The overall assembly is very compact with an area of only 6 mm × 8 mm as seen in the right part of Fig. 1 and corresponding to the schematic shown in the left part. Such a small assembly can fit a very small package whose dimensions are mainly limited by the electrical interface. SOI chip 8 mm 6 mm PD array TIA Signal Input Port LO Input PortFig. 1. Schematics of the coherent receiver (left) and picture of the coherent receiver assembly (right). Optical characterizationTwo continuous-wave (CW) optical signals were injected at the signal and LO ports with ...