Abstmct-Cyclic redundancy check (CRC) is one of the most important error-detection schemes used in digital communications. In this paper, a new parallel algorithm for CRC generation and its software as well as hardware implementation is described. For the software implementation, this paper has focussed on the 32-bit CRC used in Ethernet, computed on a general purpose PowerPC microprocessor with the new AltiVec technology. A speedup by a factor of 4.57 over the standard table-lookup algorithm was obtained. A hardware implementation of the algorithm is then discussed, which yields an unlimited speed-up potential over the bit-wise serial algorithm.

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The time-symmetric block time-step (TSBTS) algorithm is a newly developed efficient scheme for N-body integrations. It is constructed on an era-based iteration. In this work, we re-designed the TSBTS integration scheme with dynamically changing era size. A number of numerical tests were performed to show the importance of choosing the size of the era, especially for long time integrations. Our second aim was to show that the TSBTS scheme is as suitable as previously known schemes for developing parallel N-body codes. In this work, we relied on a parallel scheme using the copy algorithm for the time-symmetric scheme. We implemented a hybrid of data and task parallelization for force calculation to handle load balancing problems that can appear in practice. Using the Plummer model initial conditions for different numbers of particles, we obtained the expected efficiency and speedup for a small number of particles. Although parallelization of the direct N-body codes is negatively affected by the communication/calculation ratios, we obtained good load balance results. Moreover, we were able to conserve the advantages of the algorithm (e.g., energy conservation for long-term simulations).