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Low-power-dissipation microprocessors, which vary the frequency and power-supply voltage depending on system loads, have recently been developed for portable electric devices. They require cache technology to ensure a wide operating-voltage range to enhance performance. A universal-Vdd 32kB four-way-set-associative embedded cache test chip uses 0.18µm enhanced CMOS technology and continuously operates from 0.65V to 2.0V. Operating frequency and power are from 120MHz at 1.7mW and 0.65V to 1.04GHz at 530mW and 2.0V. Cache performance is attained using voltage-adapted timing generation with plural dummy cells and a lithographical-symmetric memory cell (LS-cell).As power supply voltage is reduced, a lower threshold voltage becomes preferable for high-speed operation. However, the threshold voltage of memory cells must be kept at a minimum of 0.5V to reduce the leakage current and to maintain static-noise margins. On the other hand, the threshold voltage of peripheral circuits is reduced to 0.4V to attain high-speed operation at low voltage operation. This threshold voltage difference could cause activation failure of a sense amplifier in wide-supply-voltage operation. To avoid such failure, voltage-adapted timing generation uses plural dummy cells. The timing pulse is used for activating the sense amplifier and for resetting word lines. Figure 11.1.1a shows a block diagram of a half side of the cache quadrant. The quadrant is composed of 256 word lines by 256 bit columns. When the clock signal changes from 'L' to 'H', the signal (dec_en), generated in a D-flip flop, activates predecoders and a word line. Then signal voltages appear on bitline pairs.The signal (dec_en) also activates the dummy word line, which runs parallel to the bitline, and the twelve dummy cells (DCs) on the dummy column drive the dummy bitline, whose capacitance is identical to that of the regular bitline. In these circuits, no extra area is needed for the dummy word line even if plural dummy cells are used. The detailed circuits of the dummy-column cell and edge-column cell are shown in Figure 11.1.1b. The dummy column is used as the electrical dummy column while the edge column is used as the optical dummy. As a result, the layouts of the diffusion layer and poly silicon layer in the SRAM array, the dummy column, and the edge column are kept regular. The dummy-cell current is identical to the memory-cell current in a regular SRAM array. A timing pulse, (voltage-adapted pulse) is used as the sense-amplifier enable signal, (sa_en), the precharge reset signal, (pc_en), and the word-line-reset signal. The word-line-reset is only in the predecoder, so the area for reset is minimized. Figure 11.1.2 shows timing diagrams of the cache. At 2.0V, bitline-drive time is 24% of the total access time. However, bitline-drive time increases to 48% at 0.65V because of the memory cell with high-Vt MOS. Here, high-Vt dummy cells drive a part of the timing-generation path, so the sense amplifier is activated suitably even at low voltage. Although a dummy cell stru...