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This paper presents the fabrication and reduction of noise voltage power spectral density (PSD) of Si x Ge y O 1−x− y uncooled infrared microbolometers with four different compositions. The noise reduction was achieved by passivating Si x Ge y O 1−x− y with Si 3 N 4 layers and by annealing the devices in vacuum at 200°C, 250°C, or 300°C with different time intervals from 1 to 5 h. The voltage noise PSD was measured with a bias current between 0.07 and 0.6 µA before and after annealing. The lowest measured noise voltage PSD before annealing was on devices with Si 0.053 Ge 0.875 O 0.072 and Si 0.041 Ge 0.902 O 0.057 films. They were 7.42 × 10 −15 and 2.07 × 10 −14 V 2 /Hz at 23 Hz, respectively. The corresponding 1/f -noise coefficients, K f , of the devices were 3.65 × 10 −14 and 3.01 × 10 −14 , respectively.The voltage noise PSD was reduced as the annealing time and temperature were increased. The lowest measured noise was 1.96 × 10 −14 V 2 /Hz at the corner frequency, 12 Hz, on a device with Si 0.034 Ge 0.899 O 0.067 film annealed at 300°C for 4 h, before annealing the noise was 4.09 × 10 −13 V 2 /Hz at 12 Hz. This corresponds to a factor of 24 reduction of noise. The testing results demonstrate that annealing at higher temperature 300°C reduced the low-frequency voltage noise PSD more than that of 200°C and 250°C temperatures.

This paper presents the formation and the characterization of silicon germanium oxide (SixGeyO1-x-y) infrared sensitive material for uncooled microbolometers. RF magnetron sputtering was used to simultaneously deposit Si and Ge thin films in an Ar/O2 environment at room temperature. The effects of varying Si and O composition on the thin film's electrical properties which include temperature coefficient of resistance (TCR) and resistivity were investigated. The highest achieved TCR and the corresponding resistivity at room temperature were -5.41 %/K and 3.16×103 ohm cm using Si0.039Ge0.875O0.086 for films deposited at room temperature.

We have developed a general purpose evolutionary algorithm testbed (GPeat) that allows evolutionary algorithm designers to quickly and with minimal hardware knowledge move their algorithms into hardware. A user programs the testbed through a graphical user interface (GUI) that lets the user choose system parameters such as types and combinations of crossovers and mutations, initial population descriptions, fitness function rules, criteria for selection and elitism rates. A variety of sensors or computer connections can be made to the testbed so that both intrinsic and extrinsic runs can be carried out. Outputs of the testbed can likewise be computer or device directed. Use of the GUI requires minimal knowledge of hardware and connecting sensors and output devices to the board requires only the ability to identify basic device characteristics (i.e. voltage or current output, analog or digital output). In this first version, sensor inputs, fitness/chromosome value pairs, generated initial values, selected outputs are dumped to a file on the computer for analysis. New evolutionary algorithm specific hardware structures have also been developed which can provide faster run times than direct FPGA implementations. This tool will allow quick prototyping for those wanting to move their algorithms from the computer to the real world, the option to use the hardware as a debugging tool or as the final embedded, portable evolutionary algorithm hardware system.