Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical synthesis issues for such systems. Such efforts showed a significant reduction in interconnect lengths. In order to effectively synthesize designs for 3D systems, it is necessary to take layer assignment for resources into consideration at higher levels of the design abstraction. We address the layer assignment problem as a part of a physical aware behavioral synthesis flow. We propose a 0-1 linear program formulation to perform simultaneous and optimal scheduling, binding and layer assignment for synthesizing designs for three-dimensional vertically integrated systems. The objective is to minimize inter-stratal via and the interconnect length in the critical path while taking thermal gradient between layers into account (which has been shown to be of particular concern for 3D systems). Floorplanning is performed for the synthesized design in order to estimate interconnect lengths. Results show a reduction of approximately 37% in total interconnect lengths on an average, compared to a traditional two-dimensional implementation when 2-5 layer implementations are examined.

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Traditional application specific synthesis systems for DSP rely on a predesigned library of components. Designs in the DSP domain often involve constant operands. Using off-the-shelf library components for such designs can be wasteful in terms of area, power and timing. Operations involving constant operands are possible candidates for reduction based on partial evaluation. Classical logic synthesis is often incapable of performing reductions because of component sharing (typically decided during high level synthesis) between regular operations and those involving constant operands, which prevent minimizations during this phase. In this paper we propose a methodology for performing on-demand component reduction using partial evaluation during synthesis of application specific DSP circuits. The simplified components have better characteristics compared to their unreduced counterparts in terms of both delay and power. Use of reduced components in the synthesis loop showed a system wide improvement in performance, area and power for the synthesized designs for a variety of benchmark DSP circuits.