The electronic structures of clean InAs(lOO) surfaces have been investigated by in situ high-resolution electron-energy-loss spectroscopy. Intrinsic electron accumulation layers with carrier densities strongly depending on the surface reconstruction are formed on both As-stabilized and In-stabilized surfaces. The correlation between the surface electron densities and the surface reconstructions suggests that electrons in the accumulation layers are induced by the donorlike intrinsic surface states of InAs whose energy spectrum is determined by the surface reconstructions.It is well known that an electron accumulation layer is easily formed on InAs surfaces. Recently, this surface accumulation layer has attracted much attention because the high density of electrons on the surface has great technological importance, such as the formation of nonalloyed Ohmic contacts 1 and the realization of the three-terminal Josephson devices. 2 It is, however, not clear whether an intrinsic electron accumulation layer is present even on clean InAs (100) surfaces and how it is related with surface atomic configurations.In this work, we studied the electronic structure of both As-stabilized and In-stabilized clean InAs(100) surfaces with in situ high-resolution electron-energy-loss spectroscopy (HREELS). By analyzing the HREELS spectra, it is found for the first time that electron accumulation layers are formed on both As-stabilized and In-stabilized surfaces and, furthermore, that the electron density in the accumulation layer changes reversibly with surface reconstructions. The origin of such electron accumulation layers is discussed.HREELS is a very powerful tool to investigate semiconductor surfaces because it gives us rich information on the surface vibrational excitations which extend into semiconductors by several tens of nanometers. To pursue HREELS measurements, however, it is essential to prepare clean and undamaged semiconductor surfaces. Such techniques as cleaving, 3,4 ion bombardment and subsequent annealing, 5,6 and arsenic deposition 7,8 were used in the previous works. With these methods, however, it is difficult to obtain clean and undamaged InAs(lOO) surfaces with high reproducibility. To overcome this difficulty, the HREELS system is connected with a molecular-beam-epitaxy (MBE) chamber under an ultrahigh-vacuum condition (<3xlO~8 Pa). This configuration keeps the surface contamination negligibly small during measurements [<0.4 L (1 L = 10~6 Torrs) for 2 h] and allows us to investigate clean surfaces.The As-stabilized undoped InAs(100) surfaces were prepared as follows: 0.3-0.5-^um-thick undoped «-type InAs layers were grown on undoped InAs (100) sub-strates by MBE. The bulk electron density in the MBEgrown InAs layer is less than 2xl0 16 cm" 3 . The substrate temperature during the growth was set at 450-490 °C. The As-stabilized surfaces were obtained by cooling the arsenic-stabilized (2x4) reconstructed surfaces down to room temperature in an AS4 flux of -10 15 cm~2s _1 . During the cooling process, the reflec...

We propose a method to evaluate the carrier transport properties in the inversion layer of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) experimentally. Our approach differs from conventional methods, which have adjusted the parameters in conventional mobility models. Intrinsic phonon-limited mobility (μ phonon ) in the SiC MOSFET was observed by suppressing the severe impact of Coulomb scattering on the SiC MOS inversion layer by lowering the acceptor concentration (N A ) of the p-type well region to the order of 10 14 cm −3 . In this study, we investigated the carrier transport properties in the inversion layer of Si-face 4H-SiC MOSFETs with nitrided oxide. It is revealed that the μ phonon of the SiC MOSFET is a quarter or less than the conventionally presumed values. Additionally, surface roughness scattering is found not to be the most dominant mobility-limiting factor even at high effective normal field (E eff ) for the SiC MOSFET. These results demonstrate that conventional understanding of carrier scattering in the SiC MOS inversion layer should be modified, especially in the high E eff region.

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CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also