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obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/). Abstract-First a new high performance robust latch (referred to as HiPeR latch) is presented, that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed, that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good tradeoffs in terms of performance, robustness and cost, our proposed latches are particularly suitable to be adopted on critical paths.

In this paper we address the issue of analyzing the effects of negative bias temperature instability (NBTI) on ICs' soft error susceptibility. We show that NBTI reduces significantly the critical charge of nodes of both combinational and sequential circuits during their in-field operation. Furthermore, we prove that combinational circuits present a higher relative reduction of node critical charge than sequential ones. Therefore, as an IC ages, the soft-error susceptibility of its combinational parts will increase much more than that of its sequential parts. This poses new challenges to ICs' soft error susceptibility modeling, mandating a time dependent modeling (in contrast to the static modeling broadly considered till now), and a diverse time dependent modeling for their combinational and sequential parts

obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk TVLSI-00149-2014 1  Abstract-We address the problem of modeling the thermal behavior of photovoltaic (PV) cells undergoing a hot-spot condition. In case of shading, in fact, PV cells, may experience a dramatic temperature increase, with consequent reduction of the provided power. Our model has been validated against experimental data, and has highlighted a counterintuitive PV cell behavior, that should be taken into account to improve the energy efficiency of PV arrays. Then, we propose a hot-spot detection scheme, enabling to identify the PV module that is under hot-spot condition. Such a scheme can be used to avoid the permanent damage of the cells under hot-spot, thus their drawback on the power efficiency of the entire PV system.