In a VHDL-based design flow for application speciJic integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The PTT4 Standard includes specialized routines for describing behavior and timing of ASIC cells and integrates backannotation via Standard Delay Format (SDF)). One of the key issues of the VITAL initiative was to accelerate simulntion performance at gate level by allowing only a restricted set of VHDL. In this papec we present an eficient implementation of the VITAL-Standard in our objectoriented, event-driven logic simulation tool OLIVI A. First pmmising results concerning simulation performance compared to conventional VHDL-Simulators are given.