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Embedded compilable SRAMs using set sense amp (SSA) timing circuits with variable delays that can be selected during built-in self-test (BIST) are described. The primary purpose of the variable delays is to detect weak cells and AC defects during self test by reducing the "set sense-amp" (SSA) delay, and thereby reducing the signal margin. The weak cells can then be permanently replaced by redundant cells. The variable delay feature is also a powerful characterization tool for new array designs. IntroductionShipped product quality detractors due to AC defects in memories is a long-standing but growing problem for test in the semiconductor industry (I). IBM ASIC embedded compilable SRAMs are self-timed, such that the delay of the timing signal for setting the sense amp is generated internally, and therefore runs at fill speed even during low frequency testing. This provides good immunity to AC defects, as cells that do not work at full speed generally do not generate enough signal margin to be read correctly during all test patterns. However, the incidence of weak SRAM cells is growing due to the limitations of scaling and the increasing performance demands on embedded SRAM arrays. The resolution limits of sub-wavelength lithography leads to degraded tolerances of the features in the SRAM array, while the threshold voltage variability inherent in very small CMOS devices results in a wide distribution of drive strength in the SRAM cells (2). The requirement for high performance is motivating designers to reduce the signal margin as much as possible to improve delays. The combination of increasing AC defects with reduced signal margin increases the probability that a weak cell will marginally pass BIST testing, but will subsequently fail in the field.