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An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed. IntroductionThe last few decades have seen an astonishing increase in the functionality of computational systems. This capability has been driven by the scaling of semiconductor devices, which has enabled the number of transistors on a single chip to grow at a geometric rate, following Moore's Law [1]. In particular, the scaling of silicon metal-oxide semiconductor field-effect transistors (MOSFETs) [2] drives the effort to continue this trend into the future.However, several serious roadblocks exist. The first is the difficulty and expense of continued lithographic scaling, which could make it economically impractical to scale devices beyond a certain pitch. The second is that even if lithographic scaling can continue, the power dissipated by the transistors will bring clock frequency scaling to a halt. In fact, it could be argued that clock frequency scaling has already stopped, and microprocessor designs have increasingly relied on new architectures to improve performance. These factors suggest that in the near future, it will no longer be possible to improve system performance through scaling alone, and that additional methods to achieve the desired enhancement will be needed. Three-dimensional (3D) integration technology offers the promise of being a new way of increasing system performance, even in the absence of scaling. This promise is due to a number of characteristic features of 3D integration, including decreased total wiring length (and thus reduced interconnect delay times), a dramatically increased number of interconnects between chips, and the ability to allow dissimilar materials, process technologies, and functions to be integrated. Motivation for 3D integration

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