Electrically pumped lasing from Germanium-on-Silicon pnn heterojunction diode structures is demonstrated. Room temperature multimode laser with 1mW output power is measured. Phosphorous doping in Germanium at a concentration over 4x10¹⁹cm^-3 is achieved. A Germanium gain spectrum of nearly 200nm is observed.

Graphene is an ideal material for optoelectronic applications. Its photonic properties give several advantages and complementarities over Si photonics. For example, graphene enables both electro-absorption and electro-refraction modulation with an electro-optical index change exceeding 10 −3 . It can be used for optical add-drop multiplexing with voltage control, eliminating the current dissipation used for the thermal detuning of microresonators, and for thermoelectric-based ultrafast optical detectors that generate a voltage without transimpedance amplifiers. Here, we present our vision for graphene-based integrated photonics. We review graphene-based transceivers and compare them with existing technologies. Strategies for improving power consumption, manufacturability and wafer-scale integration are addressed. We outline a roadmap of the technological requirements to meet the demands of the datacom and telecom markets. We show that graphene based integrated photonics could enable ultrahigh spatial bandwidth density , low power consumption for board connectivity and connectivity between data centres, access networks and metropolitan, core, regional and long-haul optical communications.Photonics is poised to play an increasingly important role in ICT ( Fig. 1a), since the fixed high capacity links are largely based on photonic technologies. Photonic devices need to support ultra-large bandwidth operation, for example, 200 Tb s−1 in a single fibre[9] and >10 Tb s −1 cm −2 in integrated Si photonics chips [10]. To achieve this, the key components of Si photonics, photodetectors and modulators, need very high performances in terms of speed (≥25 Gb s −1 ), footprint (<1 mm 2 ), insertion loss (<4 dB), manufacturability (>10 6 pieces per year) and power consumption (<1 pJ bit −1 ). To date, these requirements have not been fulfilled in one system [11]. Furthermore, in terms of production volumes, photonics is not yet comparable to microelectronics [12], even if the increase in demand for optical networks would, by 2021, lead to an average global Internet Protocol (IP) traffic of 3.3 ZB (zettabytes), corresponding to an average usage data rate of ~800 Tb s −1 (refs[13,14]). In the context of the IoT[7], other applications, including infrared (IR) sensors, biosensors, environmental sensors, metrology, quantum communications and machine vision, will require even larger production volumes [13,15].The telecom network can be divided into three segments: access, aggregation and core (Fig. 1a). The access network is the interface between subscribers and the immediate service provider. The aggregation network aggregates all the input data streams from tributary access networks, converging towards the higher-level core network. The aggregation network includes local and metropolitan networks, which then converge to regional networks. A local area network (LAN) interconnects computers within a limited area, such as a residence, school, laboratory, university or office building. A metropolitan area network (MAN) interconnects us...

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We present a micrometer scale, on-chip integrated, plasmonic enhanced graphene photodetector (GPD) for telecom wavelengths operating at zero dark current. The GPD is designed and optimized to directly generate a photovoltage and has an external responsivity∼12.2V/W with a 3dB bandwidth∼42GHz. We utilize Au split-gates with a∼100nm gap to electrostatically create a p-n-junction and simultaneously guide a surface plasmon polariton gap-mode. This increases light-graphene interaction and optical absorption and results in an increased electronic temperature and steeper temperature gradient across the GPD channel. This paves the way to compact, on-chip integrated, power-efficient graphene based photodetectors for receivers in tele and datacom modules.The ever-growing demand for global data traffic[1] is driving the development of next generation communication standards [2,3]. The increasing numbers of connected devices[4], the need for new functionalities, and the development of high-performance computing [5,6] require optical communication systems performing at higher speeds, with improved energy-efficiency, whilst maintaining scalability and cost-effective manufacturing. Si photonics[7-9] offers the prospect of dense (nanoscale) integration[10] relying on mature, low-cost (based on complementary metal-oxide-semiconductor (CMOS) fabrication processes) manufacturing [8,9], making it one of the key technologies for short-reach (<10km) optical interconnects[11] beyond currently employed lithium niobate[12] and indium phosphate[13]. A variety of functionalities have been developed and demonstrated in Si photonics for local optical interconnects[11]. Electro-optic modulators based on carrier-depletion (phase-modulation) in Si[14, 15] or the Franz-Keldysh effect[16] (amplitude-modulation) in strained Si-Ge[17, 18] encode information into optical signals at telecom wavelengths (λ =1.3-1.6µm). On the receiver side, Ge[19] or bonded III-V[20, 21] photodetectors (PD) are needed for optical-to-electrical signal conversion, since the telecom photon energies are not sufficient for direct (band-to-band) photodetection in Si[22].On-chip integrated Ge PDs [23][24][25][26][27] are standard components in Si photonics foundries [8,9,22]. Their external responsivities (in A/W), R I = I ph /P in , where I ph is the photocurrent and P in is the incident optical power, can exceed 1A/W [8,23] and their bandwidth can reach 60GHz [25][26][27]. Following the development of high temperature (> 600 • C) [19] heterogeneous integration of Ge-on-Si using epitaxial growth and cyclic thermal annealing [19,28,29], the concentration of defects and threading dislocations in Ge epilayers and at Si/Ge interfaces can be reduced [19], resulting in low (<10nA[9, 27]) dark current in waveguide integrated Ge p-i-n photodiodes [24,27]. However, Ge-on-Si integration is a complex process [19,22,29], as the lattice mismatch between Si and Ge [19], ion implantation [23,25], thermal budget (i.e. thermal energy transfer to the wafer) management [22], and the non-plan...

IntroductionCVD synthesis of graphene on catalytically-active substrates has emerged as the most promising approach for large-area production of graphene [1] . The self-limiting nature of CVD growth on metals such as copper (Cu) and platinum allows synthesis of large-scale homogeneous films of monolayer graphene. However, electrical characterization of polycrystalline samples of CVD graphene reveals that the presence of grain boundaries causes significant degradation of the electric performance, compared to pristine material obtained by mechanical exfoliation of flakes [2] . As demonstrated initially by Petrone et al [3] , samples fabricated using single-crystals of CVD graphene can have electrical performance comparable to that of exfoliated flakes [4] . Furthermore, recent reports have shown that by fully encapsulating CVD graphene with suitable materials such as hexagonal boron nitride (h-BN), low-temperature charge carrier mobility above 300 000 cm 2 / V s [5] or even 3 000 000 cm 2 / V s [6] can be achieved.Over the last few years the synthesis of large-crystal graphene has attracted a huge scientific interest, with significant advances in the achievable crystal size [7][8][9][10] . Recent work has reported single-crystals of graphene measuring 1 cm [10] and, using copper/nickel alloy as the growth substrate, even 4 cm [11] . Inevitably, these approaches still produce randomlydistributed crystals of graphene, which limits their applicability to scaled production of graphene devices. Furthermore, the commonly-used transfer methods either allow scalability while introducing significant performance degradation, or are limited to transferring areas of several tens of µm 2 [5] .For many applications the size of individual graphene devices is limited to tens or hundreds of microns, easily achievable by the current methods of single-crystal synthesis, however, ran-dom spatial distribution of graphene crystals in such samples makes polycrystalline graphene preferable for wafer-scale integration. This issue could be mitigated by selectively predetermining the nucleation sites for graphene crystals according to the target architecture, which could allow the fabrication of large and complex circuits utilising completely monocrystalline graphene. Patterned growth using polymer-based nucleation seeds was first reported by Wu et al [12] , however, only high-density arrays of 10-20 µm crystals were demonstrated. Arrays of similar dimensions were recently presented by Song et al, using poly(methyl methacrylate) (PMMA) seeds to nucleate graphene on top of CVD-grown h-BN [13] .In this work we present a method to selectively pattern the Cu growth substrate using chromium (Cr) nucleation seeds, which allows deterministic nucleation of large-crystal graphene, measuring several hundred microns. The nucleation density is highly-controlled by the combined use of natively oxidised Cu foils, non-reducing annealing and sample enclosure [14] , and measuring as low as 10 crystals per mm 2 . We also demonstrate a clean semi-dry tran...