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This paper presents a Verilog-A implementation of three different energy efficient architectures of Successive Approximation Register (SAR) analog-to-digital converter (ADC) namely SAR ADC with monotonic capacitor switching DAC, SAR ADC with split-monotonic capacitor switching DAC and SAR ADC with bypass window technique. These architectures were constructed for a resolution of 4 bits. Simulation results of all the three were compared to analyze the convergence of output nodal voltage and the reduction in switching activity. SAR ADC with bypass window technique was observed to be efficient with a switching activity of 3 for a switching activity of 4 in other two architectures. The limitations of this architecture were studied and a new architecture was proposed overcoming the limitations. Verilog-A implementation was carried out for the proposed architecture. From the simulation results it was observed that the proposed architecture retained the functionality of existing architecture except for a specific input combination where the existing architecture was less accurate. Result from the proposed architecture was 90.9% more accurate than the existing architecture.

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