This work describes an orthogonal array (OA8) designed experiment involving several insitu process perturbations during oxidation to develop a 90 Å gate oxide for 0.5μm CMOS technology. The biggest impactors were (i) the insitu preoxidation anneal at oxidation temperature, Tox, (ii) 90% N2 dilution of the ambient during ramp-up, and (iii) lowering the Tox to 850°C. Significant improvements in leakage, breakdown, and wear-out characteristics of the oxide are probably due to the reduction of poor quality ramp oxide grown by 90% N2 dilution and improved Si/SiO2 interfacial substructure attained by the insitu preoxidation anneal.

Articles you may be interested inOptimization of gate dopant concentration and microstructure for improved electrical and reliability characteristics of ultrathin oxides and N2O oxynitrides This works describes the development of a robust high quality N 2 O/O 2 -grown thin gate oxide for sub-0.5 m complementary metal-oxide semiconductor technology. Improvements in gate oxide quality ͑leakage D 0 , breakdown V bd , and wearout N bd ͒ have been attained without compromising on interface-state density ͑D it ͒ of these oxides. Such improvements have been attributed to the light nitrogen incorporation in SiO 2 near the Si/SiO 2 interface. Optimum lower thermal budget N 2 O/O 2 oxidation process has been achieved by using a N 2 O/O 2 ratio of one in the oxidant ambient.