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International audienceWe report a study of resistive switching in a silicon-based memristor/resistive RAM (RRAM)device in which the active layer is silicon-rich silica. The resistive switching phenomenon is anintrinsic property of the silicon-rich oxide layer and does not depend on the diffusion of metallicions to form conductive paths. In contrast to other work in the literature, switching occurs inambient conditions, and is not limited to the surface of the active material. We propose a switchingmechanism driven by competing field-driven formation and current-driven destruction offilamentary conductive pathways. We demonstrate that conduction is dominated by trap assistedtunneling through noncontinuous conduction paths consisting of silicon nanoinclusions in a highlynonstoichiometric suboxide phase. We hypothesize that such nanoinclusions nucleate preferentiallyat internal grain boundaries in nanostructured films. Switching exhibits the pinched hysteresis I/Vloop characteristic of memristive systems, and on/off resistance ratios of 104:1 or higher can beeasily achieved. Scanning tunneling microscopy suggests that switchable conductive pathways are10 nm in diameter or smaller. Programming currents can be as low as 2 lA, and transition timesare on the nanosecond scale

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Resistive switching in a metal-free silicon-based material offers a compelling alternative to existing metal oxide-based resistive RAM (ReRAM) devices, both in terms of ease of fabrication and of enhanced device performance. We report a study of resistive switching in devices consisting of non-stoichiometric silicon-rich silicon dioxide thin films. Our devices exhibit multi-level switching and analogue modulation of resistance as well as standard two-level switching. We demonstrate different operational modes that make it possible to dynamically adjust device properties, in particular two highly desirable properties: nonlinearity and self-rectification. This can potentially enable high levels of device integration in passive crossbar arrays without causing the problem of leakage currents in common line semi-selected devices. Aspects of conduction and switching mechanisms are discussed, and scanning tunnelling microscopy (STM) measurements provide a more detailed insight into both the location and the dimensions of the conductive filaments.

We validate for the first time the phenomenological phonon confinement model (PCM) of H. Richter, Z. P. Wang, and L. Ley [Solid State Commun. 39, 625 (1981)] for silicon nanostructures on the sub-3 nm length scale. By invoking a PCM that incorporates the measured size distribution, as determined from cross-sectional transmission electron microscopy (X-TEM) images, we are able to accurately replicate the measured Raman line shape, which gives physical meaning to its evolution with high temperature annealing and removes the uncertainty in determining the confining length scale. The ability of our model to explain the presence of a background scattering spectrum implies the existence of a secondary population of extremely small (sub-nm), amorphous silicon nanoclusters which are not visible in the X-TEM images. Furthermore, the inclusion of an additional fitting parameter, which takes into account the observed peak shift, can be explained by a size-dependent interfacial stress that is minimized by the nanocluster/crystal growth. From this we obtain incidental, yet accurate estimates for the silicon surface energy and a Tolman length, d % 0.15 6 0.1 nm using the Laplace-Young relation.