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The performance of thin f i l m interconnects is dependent upon successful interaction between design and the fabrication pmess. A well controlled process meeting properly defined design rules is necessary for a maximum performancekost ratio. In thin film interconnects, especially for high speed digital transmission, impedance control is essential.This paper deals with the functional verification of pmess tolerances to achieve the originally simulated design requirements. Variational analysis results about the nominal design value are presented and compared with initial simulation results. Interconnect capacitance and impedance variations as a function of conductor and dielectric geometry are shown.The analysis shows that the process is capable of giving an impedance within 10% of the nominal design value.