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This paper presents a one-level decomposition Haar Discrete Wavelet Transform (DWT) architecture using a 4:2 compressor and carry propagate adder. In Haar DWT architecture, coefficient multiplication is an essential operation. The Haar coefficient multiplication [Formula: see text] is implemented with [Formula: see text] multiplier and the generated partial products are represented with sign power of two (SPT) terms. The addition of SPT terms is computed with a 4:2 compressor and the final sum is computed with CPA. A [Formula: see text] multiplier with 4:2 compressor technique is used to improve energy and delay. Compared to the previous architectures, the proposed architecture gives reduction in area, power, and delay. The proposed Haar wavelet architecture is implemented in gate-level Verilog HDL and synthesized with UMC 90-nm technology using Cadence RC compiler. When compared to the existing designs, the proposed architecture Haar DWT architecture synthesis results show reduction in latency of 32.32% and 31.46% of circuit area.

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