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Low scalability and power efficiency of the shared bus in SoCs is a motivation to use on chip networks instead of traditional buses. In this paper we have modified the Orion power model to reach an analytical model to estimate the average message energy in KAry n-Cubes with focus on the number of virtual channels. Afterward by using the power model and also the performance model proposed in [11] the effect of number of virtual channels on Energy-Delay product have been analyzed. In addition a cycle accurate power and performance simulator have been implemented in VHDL to verify the results.

A novel low power-delay product full adder circuit is presented in this paper. A new approach is used in order to design full-swing full adder with low number of transistors. The proposed full adder is implemented in MOSFET-like Carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that, there are substantial improvements in both power and performance of the proposed circuit compared to latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to estimate the advantages of using carbon-based transistors in digital designs over conventional silicon technology. The proposed circuit can be applied in ultra low power and very high speed applications.

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