A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.

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Voting algorithms play a significant role in most fault-tolerant and control systems so these algorithms are continually in progress and with regard to specific situations in different systems, new voting algorithms are growing and increase the reliability and fault tolerability of systems. In this paper, a new combined algorithm using a weighted voter based on Markov chain is presented that is increased the reliability of system than both of median voter and average voter. In this paper, the proposed algorithm on average weather data of a year in Tehran was tested and simulation results show the effectiveness of the method than the other methods.