Full-duplex (FD) wireless can significantly enhance spectrum efficiency but requires tremendous amount of selfinterference (SI) cancellation. Recent advances in the RFIC community enabled wideband RF SI cancellation (SIC) in integrated circuits (ICs) via frequency-domain equalization (FDE), where RF filters channelize the SI signal path. Unlike other FD implementations, that mostly rely on delay lines, FDE-based cancellers can be realized in small-formfactor devices. However, the fundamental limits and higher layer challenges associated with these cancellers were not explored yet. Therefore, and in order to support the integration with a software-defined radio (SDR) and to facilitate experimentation in a testbed with several nodes, we design and implement an FDE-based RF canceller on a printed circuit board (PCB). We derive and experimentally validate the PCB canceller model and present a canceller configuration scheme based on an optimization problem. We then extensively evaluate the performance of the FDE-based FD radio in the SDR testbed. Experiments show that it achieves 95 dB overall SIC (52 dB from RF SIC) across 20 MHz bandwidth, and an average link-level FD gain of 1.87×. We also conduct experiments in: (i) uplink-downlink networks with inter-user interference, and (ii) heterogeneous networks with half-duplex and FD users. The experimental FD gains in the two types of networks confirm previous analytical results. They depend on the users' SNR values and the number of FD users, and are 1.14×-1.25× and 1.25×-1.73×, respectively. Finally, we numerically evaluate and compare the RFIC and PCB implementations and study various design tradeoffs.

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Previously, we presented a non-magnetic, nonreciprocal N-path-filter-based circulator-receiver (circ.-RX) architecture for full-duplex (FD) wireless which merges a commutation-based linear periodically-time-varying (LPTV) non-magnetic circulator with a down-converting mixer and directly provides the baseband (BB) receiver signals at its output, while suppressing the noise contribution of one set of the commutating switches. The architecture also incorporates an on-chip balance network to enhance the transmitter (TX)receiver (RX) isolation. In this paper, we present a detailed analysis of the architecture, including a noise analysis and an analysis of the effect of the balance network. The analyses are verified by simulation and measurement results of a 65 nm CMOS 750 MHz circulator-receiver prototype. The circulator-receiver can handle up to +8 dBm of TX power, with 8 dB noise figure (NF) and 40 dB average isolation over 20 MHz RF bandwidth (BW). In conjunction with digital self-interference (SI) and its third-order intermodulation (IM3) cancellation, the FD circ.-RX demonstrates 80 dB overall SI suppression for up to +8 dBm TX average output power. The claims are also verified through an FD demonstration where a -50 dBm weak desired received signal is recovered while transmitting a 0 dBm average-power OFDM-like TX signal.

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