Distributed amplifiers (DAs) are one of the most important and common wideband amplifiers that can use various arrangements in their gain cell structure. One of the gain cells that can be effective in increasing the bandwidth of a distributed amplifier is the pseudo-differential amplifier (PDA). Although pseudo-differential distributed amplifiers (PDDAs) have a wide bandwidth and amplify DC, they have a small voltage gain. In this paper, various circuits with the same power and chip area are proposed to improve the performance of PDDAs. For evaluating and comparing the performance of the proposed circuits, they are implemented in 0.18[Formula: see text][Formula: see text]m RF-CMOS technology. The simulation results reveal that two cascaded PDDAs with three stages have a better performance than three cascaded PDDAs with two stages; in two cascaded PDDAs with three stages, a gain of 9[Formula: see text]dB can be achieved for a bandwidth of 50[Formula: see text]GHz in 0.18[Formula: see text][Formula: see text]m RF-CMOS technology. In this amplifier, parameters S[Formula: see text], S[Formula: see text] and S[Formula: see text] are [Formula: see text]12, [Formula: see text]10 and [Formula: see text]18 dB, respectively; noise figure is 4.3–5.8[Formula: see text]dB, and [Formula: see text] is +4[Formula: see text]dBm. This amplifier consumes 220[Formula: see text]mW power and has a chip area of 0.58[Formula: see text]mm2.

This study presents a CMOS distributed amplifier (DA) with pseudo differential amplifying that achieves DC-40[Formula: see text]GHz bandwidth (BW) in 0.18-[Formula: see text]m RF CMOS process. The DA with three-stage amplifying cells was proposed to improve the DA performance. The inter-stage was composed of pseudo differential amplifying for bandwidth extension. By incorporating the pseudo differential amplifier configuration and capacitor-less circuit in the stages, the DA provides average gain and high bandwidth. The simulation results showed that the DA has a S[Formula: see text] of 6.4[Formula: see text]dB, 3-dB BW from DC up to 40[Formula: see text]GHz. It also has a minimum noise figure (NF) of 4.27[Formula: see text]dB, one dB compression point (P[Formula: see text] of [Formula: see text]3.5[Formula: see text]dBm, a high reverse isolation S[Formula: see text] of less than [Formula: see text]15[Formula: see text]dB, an input return loss S[Formula: see text] and output return loss S[Formula: see text] of less than [Formula: see text]16 and [Formula: see text]12[Formula: see text]dB, respectively. It consumes 115[Formula: see text]mW and occupies a total active area of 0.27[Formula: see text]mm2.