No abstract

No abstract

No abstract

current status is presented for the development and experimental verification of 0.18 µm high voltage CMOS integrated circuits with pad-based ESD protection made with the use of lateral bipolar transistor. Developed I/O pads provide 2000 V ESD protection. Index terms -ESD protection, I/O PAD, lateral npn transistor, CMOS Maksim S. Karpovich received his M. Eng. in electronics from Novosibirsk State Technical University (Russia) in 2011. Currently he is R&D engineer of SibIS LLC.

No abstract