On-Chip TaO x-Based Non-volatile Resistive Memory for in vitro Neurointerfaces.

Embedded, low-power, fast nonvolatile memory is considered to be a viable approach to improving the performance of computing systems designed for real-time processing of the incoming information stream. Among different nonvolatile memory concepts, resistive random access memory is one of the competitive candidates because of the combination of functional properties, such as the energy per writing cycle, speed, number of switching cycles (endurance), and retention time. In this work, we explore the effect of nanopatterning of the Pt bottom electrode (BE) to control the formation, number, and size of conductive filaments in the TaO x layer in Ta/TaO x /Pt resistance switching (RS) devices integrated with field-effect transistors (the one transistor and one resistor concept). Patterning is achieved by either etching "holes" in the Pt BE or growth of Pt "pillars" on top of a flat continuous underlayer. Such nanopatterned RS devices reveal lower (∼1.2 vs ∼2.5 V) electroforming voltages and ∼10 2 times lower currents in the ON state compared to those with a nonpatterned Pt electrode, while exhibiting more than 10 5 switching cycles without any degradation as well as better device-to-device and cycle-to-cycle repeatability of electrical characteristics. The modeling of the electric-field distribution across the functional TaO x layer reveals the edge of Pt nanopillars as the most probable area for filament formation. The elemental mapping during transmission electron microscopy analysis of the patterned Ta/TaO x /Pt RS device cross section confirms that the thickness of the TaO x layer on top of the Pt "pillar" is minimal at the inclined edge. The conducting atomic force microscopy current mapping of two patterned RS devices upon electroforming and removal of the top electrode in high-and lowresistance states confirms a single conducting channel formed at the edge of the Pt electrode.

The influence of the bottom TiO 2 interfacial layer grown by atomic layer deposition on the ferroelectric properties of the TiN/ Hf 0.5 Zr 0.5 O 2 /TiN capacitors is systematically investigated. We show that the integration of the TiO 2 layer leads to an increase in the polar orthorhombic phase content in the Hf 0.5 Zr 0.5 O 2 film. In addition, the crystalline structure of the Hf 0.5 Zr 0.5 O 2 film is highly dependent on the thickness of the TiO 2 inset, with monoclinic phase stabilization after the increase of TiO 2 thickness. Special attention in this work is given to the key reliability parameters�retention and endurance. We demonstrate that the integration of the TiO 2 inset induces valuable retention improvement. Using a novel approach to the depolarization measurements, we show that the depolarization contribution to the retention loss is insignificant, which leaves the imprint effect as the root of the retention loss in TiN/TiO 2 /Hf 0.5 Zr 0.5 O 2 /TiN devices. We believe that the integration of the insulator interfacial layer suppresses the scavenging effect from the bottom TiN electrode, leading to a decrease in the oxygen vacancy content in the Hf 0.5 Zr 0.5 O 2 film, which is the main reason for imprint mitigation. At the same time, although the observed retention improvement is very promising for the upcoming technological integration, the field cycling testing revealed the endurance limitations linked to the phase transitions in the TiO 2 layer and the rise of the effective electric field applied to the Hf 0.5 Zr 0.5 O 2 film.