Multilayer capacitors consist of multiple, often hundreds of capacitors connected in parallel to maximize volumetric efficiency. As the dielectric and electrode layer thicknesses are scaled down, microstructural imperfections become increasingly influential on the device electrical performance. Specifically, the presence of nonplanar and discontinuous electrodes can lead to local field enhancements while the relative morphologies of two adjacent electrodes determine variations in the local dielectric thickness. To study the effects of electrode morphologies, an analytical approach is taken to calculate the field enhancement and leakage current with respect to an ideal parallel‐plate capacitor. It is shown that the electrode roughness causes the leakage current to increase with respect to that of the ideal flat parallel‐plate capacitor. To further include the effects of local curvature on electric field enhancements, finite element methods are used to calculate field distributions within capacitor structures containing rough interfaces and porosity. In these simulations, the effects of electrode pore diameters, dielectric layer thickness, and the amplitude and wavelength of the electrode roughness are studied.

The temperature dependence of the electrical leakage current density of chemical solution deposited BaTiO 3 films on high purity Ni foils was investigated as function of the underlying Ni microstructure. Depending on the Ni heat treatment prior to BaTiO 3 deposition, it was found that pores in the dielectric followed the profiles of the underlying Ni grain boundary grooves. The electrical properties were then characterized on capacitors with and without the presence of Ni grain boundaries. When a Ni grain boundary from the substrate was present in the capacitor used during the electrical measurements, the loss tangent of the capacitor rose rapidly for dc biases exceeding ϳ25 kV/ cm. The critical bias increases to ϳ100 kV/ cm when no substrate grain boundaries are included in the capacitor. In addition, the capacitance-voltage curves are much more symmetric when grain boundaries are absent. This disparity in the electrical behavior was analyzed in terms of the mechanisms of charge conduction across the Ni-dielectric interface. While a reverse biased Schottky emission mechanism dominates the current in areas free of Ni grain boundaries, the barrier at the cathode is ineffective when Ni grain boundaries are present in the substrate. This, in turn, leads to a larger leakage current dominated by the forward biased Schottky barrier at the anode. The results are important to both embedded and surface mount capacitors.

Multilayer ceramic capacitors (MLCCs), owing to their processing conditions, can exhibit microstructure defects, such as electrode porosity and roughness. The effect of such extrinsic defects on the electrical performance of these devices needs to be understood to achieve successful miniaturization. To understand the influence of microstructural defects on field distributions and leakage current, the three‐dimensional (3‐D) microstructure of a local region in MLCCs is reconstructed using a serial‐sectioning technique in the focused ion beam. This microstructure is then converted into a finite element model to simulate the perturbations in electric field due to the presence of electrode defects. The electric field is significantly enhanced in the vicinity of such defects, and this is expected to have a bearing on the leakage current density of these devices. To simulate the scaling effects, the dielectric layer thickness is reduced in the 3‐D microstructure keeping the same electrode morphology. It is seen that the effect of microstructure defects is more pronounced as one approaches thinner layers, leading to higher local electric field concentrations and a concomitant drop in insulation resistance.