A simple, complete, and analytical deep submicrometre SOI MOSFET model for accurate simulation of digital/analogue circuits is presented. The model was developed by using the drift-di usion equation with a modi® ed mobility formula to account for velocity overshoot, and was based on a quasi-two-dimensional Poisson' s equation. It is a charge control model, expressed as a function of inversion charge per unit area. The drain current equation has been successfully applied to model both submicron and deep-submicrometre SOI nMOSFETs with various channel lengths and a good agreement between the modelled and experimental data has been obtained. The model contains the following advanced features: (a) precise description of the subthreshold, near threshold, and above-threshold regions of operation, and I± V and G± V characteristics in the saturation region; (b) single-piece drain current equation smoothly continuous from the linear region to the saturation region; (c) consideration of the source/drain resistance; (d) inclusion of important short channel e ects such as velocity overshoot, drain induced barrier lowering and channel length modulation; (e) inclusion of the self-heating e ect due to the low thermal conductivity of the buried oxide; and (f) inclusion of the impact-ionization of MOS devices and the parasitic BJT e ect associated with drain breakdown. This model uses few ® tting parameters and can be employed in a circuit simulator to improve the convergence of simulation and computational e ciency. NomenclatureC of (C ob ) front (back) gate± oxide capacitance C d (C i, C gc ) 1-D depletion (inversion, gate-channel) capacitance E sf (E b ) front (back)-gate surface electric ® eld E y (E c ) electric (critical electric) ® eld I DS (I Dsat ) drain (saturation drain) current k B Boltzmann constant K d ( K ox ) slicon (gate oxide) thermal conductivity L(W) e ective channel length (width) N ch substrate concentration Q m inversion charge density Q mS Â (Q mD Â ) inversion charge density at the intrinsic source (drain) end q elementary charge R S ( R D ) source (drain) series resistance R th thermal resistance t si SOI ® lm thickness T l (T n ) lattice (electron) temperature U l (U n ) lattice (electron) thermal voltage V GF (V GB ) front (back) gate± source voltage V Ff (V Fb ) front (back)¯at-band voltage V T (D V T ) threshold voltage (threshold voltage reduction) V BI built-in potential of the source± substrate junction V GC gate channel voltage v c (v o c ) critical velocity (at ambient temperature) V CS (V CS Â ,VDS ) channel± source (channel± intrinsic source, drain± source) voltage ² s permittivity of silicon ¹ n (¹ o n ) non-local electron (low ® eld electron) mobility ¹ o (¹ so ) maximum low-® eld (at ambient temperature) mobilityx ,Lv,a µ ® tting constants y Sf ( y b ) front-gate (back-gate) surface potential