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The dependency of complex embedded Safety-Critical Systems across Avionics and Aerospace domains on their underlying software and hardware components has gradually increased with progression in time. Such application domain systems are developed based on a complex integrated architecture, which is modular in nature. Engineering practices assured with system safety standards to manage the failure, faulty, and unsafe operational conditions are very much necessary. System safety analyses involve the analysis of complex software architecture of the system, a major aspect in leading to fatal consequences in the behaviour of Safety-Critical Systems, and provide high reliability and dependability factors during their development. In this paper, we propose an architecture fault modeling and the safety analyses approach that will aid in identifying and eliminating the design flaws. The formal foundations of SAE Architecture Analysis & Design Language (AADL) augmented with the Error Model Annex (EMV) are discussed. The fault propagation, failure behaviour, and the composite behaviour of the design flaws/failures are considered for architecture safety analysis. The illustration of the proposed approach is validated by implementing the Speed Control Unit of Power-Boat Autopilot (PBA) system. The Error Model Annex (EMV) is guided with the pattern of consideration and inclusion of probable failure scenarios and propagation of fault conditions in the Speed Control Unit of Power-Boat Autopilot (PBA). This helps in validating the system architecture with the detection of the error event in the model and its impact in the operational environment. This also provides an insight of the certification impact that these exceptional conditions pose at various criticality levels and design assurance levels and its implications in verifying and validating the designs.

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This paper presents the best practices to carry out the verification and validation (V&V) for a safetycritical embedded system, part of a larger system-of-systems. The paper talks about the effectiveness of this strategy from performance and time schedule requirement of a project. The best practices employed for the V &Vis a modification of the conventional V&V approach. The proposed approach is iterative which introduces new testing methodologies apart from the conventional testing methodologies, an effective way of implementing the phases of the V&V and also analyzing the V&V results. The new testing methodologies include the random and non-real time testing apart from the static and dynamic tests. The process phases are logically carried out in parallel and credit of the results of the different phases are taken to ensure that the embedded system that goes for the field testing is bug free. The paper also demonstrates the iterative qualities of the process where the iterations successively find faults in the embedded system and executing the process within a stipulated time frame, thus maintaining the required reliability of the system. This approach is implemented in the most critical applications-aerospace application where safety of the system cannot be compromised. The approach used a fixed number of iterations which is set to4in this application, with each iteration adding to the reliability and safety of the embedded system. Data collected and results observed are compared with a conventional approach for the same application and it is demonstrated that the strategy proposed reduces the time taken by 50% as compared to a conventional process that attains the same reliability as required in the stipulated time.