This paper is on FPGA based emulation which is one the approaches to perform pre-silicon SoC validation, accelerate system software development and to meet time-tomarket demands. This paper presents a verification methodology of SoC and also deals with simplified implementation of complex clock designs in FPGA are presented, which needs to be skillfully handled to meet the said criteria. Each base sequential element is modified to receive a global clock, corresponding circuit clock and a data value. A base sequential element (contained in modified sequential element) transitions to a next state only after occurrence of a transition on a corresponding circuit clock and the transition to said next state may be timed according to the global clock. In this paper the results demonstrate how to reduce the register utilization, LUT utilization and the time of place and route in VLSI design.