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This article employs a nested state feedback compensation technique to a three-stage bulk-driven operational transconductance amplifier (OTA). The projected OTA circuit consists of a bulk-driven PMOS amplifier, gate-driven NMOS amplifier, and common source (CS) amplifier. The entire transistors in the amplifier core are configuredwith self-cascode transistor topology to increase its output impedance. All transistors are designed to operate in a weak inversion in order to dissipate less power. Cross-coupled transistor pair topology in the bulk-driven stage allows to improve the effective transconductance of OTA. The CS amplifier can drive a large load capacitor.  The polarities and transconductance gains of feedback blocks are controlled appropriately to obtain the desired DC gain and bandwidth. The capacitor-less compensation strategy allows the fabrication of the OTA using the minimum area. Conventional bulk-driven miler OTA, Bulk-driven stage improved indirect-feedback OTA (BSIF OTA), Gate-driven stage added bulk-driven OTA (GSIF OTA), and proposed bulk-driven OTA topologies are designed and simulated using cadence spectre tool at 25 mV supply voltage in the 65nm CMOS process. These OTA circuits are analyzed and compared in terms of parameters like DC gain, unity-gain frequency, phase margin, CMRR, power dissipated, slew rate, and input referred noise.

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