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SRAMs occupy more than 50% performance SoCs. Device variations in ad nodes limit SRAM cell performance and yiel time defines performance limited yield fo work, we estimate sensitivity of write time o to variations in different devices thr Experiments (DoE) method. We evaluate m models and estimate variation in yield for specification. This work enables a performa off and formalizes a Design for Yield (D benchmark multiple yield models and sho models for write time are more accurate. minimum required write time for different find that to achieve a target yield of 99% needs to budget a write time of 656 ps when SRAM in 65nm technology. For a target y 1Mb capacity, 573 ps write time is sufficient Keywords -Design for yield (DFY), 6T S of Experiment (DoE), Nonlinear Regression, Write Speed 2015 28th International Conference on VLSI Design