This paper describes a delta-sigma analog-to-digital converter (ADC) capable of converting input frequencies up to 250 kHz. It consists of a fifth-order switched-capacitor delta-sigma modulator and a decimation filter. Various design optimizations in the modulator are presented. The decimation filter consists of a comb filter followed by a novel, highly efficient and scalable finite impulse response filter. The ADC was implemented in 0.6-m CMOS technology. It achieves a dynamic range of 94 dB.
-In this paper, we have presented an approach to realize third order current-mode filters using CMOS current-mirrors with two different techniques. This paper presents the realization of third-order low-pass (LP) active current-mode filters using cascade technique of lossy and lossless integrators. Another important technique is the active realization of third-order low-pass filter that has been derived from the passive ladder-RLC Leapfrog filter structure. Interest in current-mode (CM) filters has been growing due to the fact that current-mode devices have wider dynamic range, improved linearity, and extended bandwidth as compared to their voltage-mode counterparts. In the sub-micron era of semi-conductor technology, the minute structure of devices causes a high electric field and thus the power supply voltage is limited to a certain low value to protect the device from destruction. Current-mode signal processing is quite attractive for operation at high frequencies and low power supply voltage operation from the viewpoint of sub-micron era. The realized filters do not contain any resistors, therefore simplifying the pattern of integrated circuits and thus reducing the chip area and the cost. The proposed circuits presented in the paper were tested in SPICE using 0.5µm CMOS process parameters provided by MOSIS (AGILENT) and the results thus obtained were in accordance with the theoretical values.
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